The present invention generally relates to semiconductor devices, and in particular to a process for fabricating a semiconductor-on-insulator (SOI) device in alignment with a device region formed in a semiconductor substrate.
With the wide-spread use of electronic apparatuses, various semiconductor devices having various characteristics are required. In the display devices, for example, semiconductor devices having a high breakdown voltage are needed to drive the display driver with a high drive voltage. For this purpose, semiconductor-on-insulator (SOI) devices that are formed on an insulating substrate are well suited, as such a semiconductor device achieves a high breakdown voltage of 100-200 volts, without using a complex isolation structure.
In the SOI devices driven by high voltage, there arises a problem of backchannel effect wherein the channel region causes an inversion along the boundary thereof with the insulating substrate due to the large source or drain voltage. It should be noted that the surface of the substrate in contact with the channel region is maintained generally at the ground level. In order to eliminate the foregoing backchannel effect, a structure is proposed wherein the insulating substrate is provided on a semiconductor substrate, and a diffusion region is formed in the semiconductor substrate in correspondence to the SOI device. BY suitably biasing the diffusion region as a second gate, one can eliminate the formation of inversion layer and thus the backchannel effect.
In forming such an SOI device, it is necessary to provide a substrate structure wherein an insulator layer is provided on a semiconductor substrate as the insulating substrate, a diffusion region formed in correspondence to where the SOI device is to be formed as the second gate for eliminating the backchannel effect, and a single crystal semiconductor layer grown on the insulator layer as the active layer of the semiconductor device. In such a three-layer substrate, it will be understood that an alignment mark is necessary on the surface of the single crystal semiconductor layer in order to achieve the alignment of the SOI device that is formed in the upper, single crystal semiconductor layer with respect to the corresponding diffusion region formed in the lower semiconductor substrate.
FIGS. 1(A) and 1(B) show a conventional three-layer substrate body 10 respectively in a plan view and a cross sectional view.
Referring to the drawings, the three-layer substrate body 10 comprises a semiconductor substrate 11 doped, for example, to the p-type, an insulator layer 22 provided on the substrate 10 as the insulating substrate of SOI device, and a single crystal silicon layer 24 grown further on the insulator layer 22 as the active layer of the SOI device. In the substrate 11, a diffusion region 20 is formed as the second gate of the SOI device for eliminating the backchannel effect.
In order to establish a proper alignment between the SOI device and the underlying diffusion region, there is provided an alignment mark 16 on the surface of the substrate body 10 as shown in the plan view of FIG. 1(A). In the cross sectional view, the alignment mark 16 is formed with a predetermined relationship to the diffusion region 20 such that the SOI device can be formed on the single crystal silicon layer 24 exactly in correspondence to the diffusion region 20.
The three-layer semiconductor body 10 may be formed by the processes of: forming a thin oxide layer (not shown) on the surface of the semiconductor substrate 11; providing a photoresist layer (not shown) on the oxide layer; patterning the photoresist layer to form an opening exposing the surface of the oxide layer in correspondence to where the alignment mark 16 is to be formed; forming the alignment mark 16 by etching while using the photoresist layer as a mask such that the alignment mark penetrates through the oxide layer and invades into the substrate 11; removing the photoresist layer; providing a second photoresist layer; patterning the second photoresist layer using the alignment mark to expose a region where the diffusion region 20 is to be formed, applying an ion implantation process using the photoresist as the mask; removing the second photoresist layer; oxidizing the semiconductor body 10 to grow a thin oxide layer comprising the insulator layer 22; depositing a polysilicon layer (not shown) on the insulator layer 22, and annealing the polysilicon layer to form the single crystal layer 24. Thereby, the alignment mark 16 is transferred to the surface of the single crystal layer 24 as a depression. Using this depression as the alignment mark, the single crystal layer 24 is patterned and the SOI device is formed in correspondence to the diffusion region 20. By using the diffusion region 20 as the second mask, one can eliminate the problem of the backchannel effect as described previously.
Several processes are available for annealing the polysilicon layer to form the single crystal silicon layer 24. For example, one can employ the laser beam heating process to cause the polysilicon layer to melt and crystallize into the single crystal layer. This process, however, has a problem in the quality of the resulting single crystal silicon layer 24, as the silicon layer 24 thus formed tends to exhibit a deterioration in the drain breakdown voltage, an increase in the on-state resistance, variations in the device characteristics, and the like, due to the sub-grain boundaries included in the layer 24. In the laser beam melting, it will be understood that the formation of uniform, defect-free single crystal layer throughout the surface of the substrate body 10 is extremely difficult because of the lack of the epitaxial relationship.
In order to circumvent the foregoing problem, use of a process called zone-melting-recrystallization (ZMR) is proposed.
FIGS. 2(A) and 2(B) show a conventional ZMR process. Referring to the plan view of FIG. 2(A), the insulator layer 22 is formed to expose a marginal part of the semiconductor substrate 11 that may have a (001) oriented surface and a thickness of about 500 .mu.m. On the insulator layer 22, a polysilicon layer 24' is deposited in contact with the exposed (001) surface of the substrate 11 as shown in the cross sectional view of FIG. 2(B) with a thickness of about 5000 .ANG. and the substrate body 10 is passed through a heating fixture including carbon strip heaters 101 and 102 as shown by the arrow in FIG. 2(A). Upon passage through the heating fixture 101 and 102, the polysilicon layer 24' is caused to melt by heating to a temperature of about 1450.degree. C. and then is recrystallized to form the single crystal layer 24. As the melting and recrystallization starts at the marginal part where the polysilicon layer 24' is in contact with the exposed (001) surface, the layer 24 has the same crystal orientation throughout the substrate body 10 and the problem of the sub-grain boundary formed in the layer 24 is eliminated.
In such a ZMR process, it will be noted that the lower carbon strip heater 102 should be driven with a power that is lower than the power used to drive the carbon strip heater 101 such that the substrate 11 is not heated excessively and the migration of impurities out of the diffusion region 20 does not occur. For example, the temperature of the substrate 11 is held at 1300.degree. C. However, such a temperature difference causes a large thermal stress in the substrate body 10 between the recrystallized silicon layer 24 and the underlying silicon substrate 11.
Further, it was found that the position of the alignment mark 16 moves laterally after the ZMR process. More specifically, the applicant of the present invention has found that the alignment mark 16 moves laterally toward the marginal area of the substrate body 10 as shown by a mark 16' in FIG. 1(A) when the ZMR process is applied. In the case of a circular substrate body 10 having a diameter of 4 inches with a pair of alignment marks 16 formed on diametrically opposing positions with a separation of 6-7 cm, the amount of movement can reach as much as 1 .mu.m for each alignment mark 16. Thereby, one encounters a problem in the alignment of the mask used for patterning the single crystal layer 24 to form the SOI device with respect to the diffusion region 20 formed in the substrate 11.
Although the cause of this phenomenon is not completely explored, it is thought probable that the polysilicon layer 24' undergoes a lateral expansion upon melting, and the alignment mark 16, formed on the surface of the layer 24', moves to the position 16' accordingly. It should be noted that silicon increases the volume thereof upon melting. Upon cooling, the molten silicon layer solidifies at about 1415.degree. C. and the relative positional relationship between the new alignment mark 16' and the original alignment mark 16 is established thereby. It should be noted that, during this process, the substrate 11 is held at about 1300.degree. C. or less to avoid the diffusion of the impurities away from the diffusion region 20. Thus, even when a shrinkage occurs in the recrystallized silicon layer 24 upon the solidification to cancel out the expansion at the time of melting, the alignment mark 16' does not return to the original position 16 because of the temperature difference between the layer 24 and the substrate 11. Thereby, it is believed, though not confirmed yet, that the substrate body 10 thus formed by the ZMR process has a cross section as shown in FIG. 2(C) wherein the alignment mark 16' in the recrystallized single crystal layer is offset laterally to the alignment mark 16 formed in the substrate 11.
When one uses the alignment mark 16' at the time of patterning the single crystal silicon layer 24 to form an SOI device, it will be understood that no proper alignment is achieved between the SOI device thus formed and the diffusion region 20 formed in the substrate 11. Thus, there arises a difficulty in achieving the elimination of the backchannel effect described previously.